1. Field of the invention
The present invention relates to a word line enable timing determination circuit of a memory device and methods of operation therefor.
2. Description of the Related Art
A pseudo static random access memory (PSRAM) internally uses a cell structure of a dynamic random access memory (DRAM), and is externally similar to a static random access memory (SRAM). A cell structure of a PSRAM includes a unit transistor and a unit capacitor, like the DRAM, and is thus termed a unit transistor random access memory (UtRAM). In these memory structures, a refresh operation is typically needed to prevent a loss of data stored in memory cells. The PSRAM includes an internal refresh oscillator to perform a refresh operation at a constant period, and may automatically perform a hidden refresh by using a refresh control pulse generated in the refresh oscillator.
When a read/write command is externally input to the PSRAM to perform a read/write operation, while a memory cell is being refreshed with the internal refresh oscillator, data of the memory cell cannot be guaranteed to execute the read/write operation. That is why a controller at the exterior of the PSRAM cannot acknowledge when a refresh operation within a memory chip is to be performed.
FIG. 1A is a timing diagram of a fixed dummy duration for a hidden refresh operation in a prior art memory device. To solve the above-described problem in a prior art memory device such as a PSRAM, a fixed dummy duration, during which the hidden refresh operation may be performed, is unconditionally guaranteed before an external read/write command is executed in a given read/write cycle. In other words, whenever a read or write command is to be executed, the fixed dummy duration is needed to guarantee the row cycle time, or ‘trc’ for hidden referesh of a word line. Thus, in the prior art PSRAM, the word line enable time for a read/write command is always delayed by the fixed dummy duration time. This may pose a substantial restriction or limit on the high-speed operational capabilities of a memory device such as a PSRAM.
In FIG. 1A, “addr” indicates an address, “WL” represents a word line, and “DQ” represents output of data. The time “tRC” represents a read cycle time, “tAA” represents an address access time, and “taa” represents a duration of time from a time enabled to a word line until an output time of data.
FIG. 1B illustrates a trc (row cycle time) for a word line of the hidden refresh in further detail. In the prior art, the dummy duration time is needed to guarantee trc for a word line of hidden refresh in a memory device such as a PSRAM. The trc (row cycle time) may be further comprised of a row active time (tRAS) and a row precharge time (tRP). As shown in FIGS. 1A and 1B, the fixed dummy duration is about equal to the trc, so as to guarantee a sufficient trc duration for a word line of hidden refresh.
FIG. 2 illustrates a circuit diagram of a prior art word line enable determination circuit in a memory device such as a PSRAM chip. Referring to FIG. 2, a word line enable determination circuit 200 includes an address transition detector (ATD) 210 for sensing a transition of an address signal addr inputted from an exterior of the PSRAM chip, and for generating an address detection pulse (PP). Circuit 200 may also include an address decoder (not shown) for decoding the address signal address so as to activate the word line. A dummy duration part 212 may delay, by a given delay time, the PP so as to output a delayed detection pulse (PUL). An automatic pulse generator (hereinafter, referred to as a ‘pulse generator’) 214 may automatically generate a delayed dummy control pulse signal (PULP) when the PUL is disabled, i.e., if the PUL goes to a low state.
Word line enable determination circuit 200 may also include a refresh cutting signal generator 216 for outputting a refresh cutting signal (NERFH) based on the received PUL. A refresh pulse signal generator 220 may generate a refresh pulse signal (SRFHP) in response to a hidden refresh signal (SRFH) that is output with a given period from an internal refresh oscillator 218. The refresh pulse signal generator 220 may cut off an output of the SRFHP in response to the NERFH. A word line enable circuit 222 may generate a word line enable duration signal (PWL) during a given time, in response to the PULP and the SRFHP, as shown in FIG. 2. The PWL and a decoded address signal (addr) may be input to a row decoder (not shown) so as to activate a word line (WL) for a read/write command. Namely, the word line is enabled during a high pulse width of the PWL, hence the PWL may be referred to as the word line enable duration signal.
The SRFH output from the internal refresh oscillator 218 may be provided to a refresh address counter (not shown), so as to perform a refresh operation of the memory cell. The dummy duration part 212 may include inverters 223 through 226 (connected in series) NOR gate 228 and inverter 229, for generating the PUL at a first pulse width, by performing a negative logical sum of the PP, which is supplied to an input terminal of inverter 223 and to NOR gate 228, as shown in FIG. 2.
The pulse generator 214 may be embodied as an automatic pulse generator that includes an inverter 232 and a NOR gate 234. The refresh cutting signal generator 216 may include inverters 236, 238 and 242 and NOR gate 240. The refresh cutting signal generator 216 outputs the NERPH in response to the received PUL, as discussed above.
The refresh pulse signal generator 220 may be embodied as a an automatic pulse generator including an inverter 244, NOR gate 246 and RS flip-flop 248. RS flip-flop 248 may be set by an output of the NOR gate 246 and reset by the NERFH. Refresh pulse signal generator 220 further includes inverter 250 for inverting an output of the RS flip-flop 248 to output the refresh pulse signal SRFHP.
The word line enable duration circuit 222 may include a NOR gate 252 for performing a negative logical sum of the PULP and the SRFHP, inverters 254, 256, 258 and 262, and a NOR gate 260. The word line enable duration circuit 222 thus generates the PWL based on the PULP and the SRFHP.
Operations of the word line enable determination circuit in the general PSRAM of FIG. 2 may be described referring to the timing diagrams of FIGS. 3 through 5. When the read/write address signal addr is input to ATD 210 and the PP is output therefrom, a duration of the PP may be extended by inverters 224, 226 and NOR gate 228 within the dummy duration determination part 212 of FIG. 2, to be output as the delayed detection pulse PUL. At this time, delay through inverters 224, 226 and the NOR gate 228 may represent a fixed dummy duration time, as shown in the PUL of FIG. 3. When the PUL is delayed by the pulse generator 214 and is generated as the delayed pulse PULP, a word line enable duration signal may be activated by the word line enable detection circuit 222, shown as PWL in FIG. 3. Thus, the timing diagram of FIG. 3 illustrates that in the prior art, word line enable timing is delayed by a fixed dummy duration time, which in FIG. 3 equals the pulse width of the PUL.
When the hidden refresh signal SRFH of a ‘low’ state is generated from the internal refresh oscillator 218, such that the fixed dummy duration is determined every read/write cycle, the RS flip-flop 248 is set, enabling word line enable duration circuit 222. At this time, memory cells within a memory cell array are refreshed by a refresh address counter operation, upon receipt of the SRFH. The RS flip-flop 248 is reset by the NERFH output from the refresh cutting signal generator 216. Thus, in a case where the prior art word line enable determination circuit 200 of FIG. 2 executes a refresh operation at a minimum tRC, the circuit 200 operates as illustrated by the timing diagram of FIG. 4. In FIG. 4, a tRC(read cycle time) is essentially equal to a tAA(address access time) in the prior art SRAM, therefore the tRC based on the circuit of FIG. 2 may be determined as 2trc(tRC=2trc).
A skew free operation is a function supported in an PSRAM. A skew free operation may be understood as an operation of ignoring a precedent arriving read/write command when two or more read/write commands are successively received by the PSRAM, in a time period in which a minimum tRC is smaller than a fixed dummy duration, such as is shown in FIG. 5. When consecutive read/write commands are received internally in the PSRAM, within a time period that is smaller than a trc duration, the preceding (i.e., first) read/write commands are ignored and not performed, so as to sufficiently guarantee the trc duration.